I’ve made significant progress porting over the rtl-sdr code. I added printfs to every function that interfaces with the USB port so that I can compare what happens. Everything seems normal, up until the gainControl function. Once there, the returns from my application are usually about one digit off of the rtl-sdr code. If anyone has any ideas, I’d love to hear them!
If there’s one thing that I was blissfully ignorant of before trying to build a spectrum analyzer, that is now an annoyance and borderline obsession, it’s phase noise. Phase noise is exactly the same as any other kind of noise, but unlike noise on a DC signal, phase noise is mode like tiny variations in the frequency of the signal.
To get a little more specific, think about phase as a quantity that describes how far along the sine wave we are at any given instant. It can be described in degrees, radians, or even if you’re a little radical, tau radians. The idea is the same. Phase increases until it “rolls over” at the end of the cycle. It looks a bit like a sawtooth wave, assuming that we’re discussing a constant frequency, unmodulated wave. Hopefully you believe me that phase noise looks just like noise superimposed on the sawtooth-shaped phase ramp.
I think the graphs above helps to illustrates the relationship between phase (above) and a sine wave (below). I’ve re-scaled the phase so that it goes from zero to one over the range of one whole number.
In the frequency domain, phase noise is a little easier to understand, and see. The graph at the head of this article is an extreme example of phase noise. Really, there are two kinds of phase noise here, and one of them we can do something about.
I tried really hard to find some nice graphics to use to describe, simply, the basic operation of a PLL-based oscillator. The best I could come up with is the above diagram. This was lifted from the Linear Technology LMX2326 PLL IC. This is the same (or damn near) as the PLL chip that’s used in the analyzer. The bottom left corner is the oscillator. All it does it generate a single frequency set by the voltage coming into pin 6. On the PLL chip, pin 2 is the output from the “charge pump,” which is how the PLL sets the tuning voltage.
Unfortunately, the PLL in the spectrum analyzer isn’t this simple (if you can call an normal PLL simple!). In the center, near the top, notice the Op-Amp. The high-side supply to this amplifier is +20 volts (at least). The reason for this is as simple as that’s what the VCO (voltage controlled oscillator) needs. It isn’t possible for the PLL to produce voltages like this, so we need this extra supply.
Now, the question is: “What happens when there’s noise on the +20 voltage supply?” The waveform on the oscilloscope above shows about 20mV of noise on the 20 volt supply. The frequency of this noise is about 20kHz. It’s no coincidence that the spacing between the peaks in the comb-like plot is about 20kHz. What’s happening is that the noise on the 20 volt supply is literally modulating the output. Incidentally, that’s exactly what you do if you want to frequency modulate something.
Now that we know what the cause is, what can we do about it? If we eliminate that noise, we can fix the problem. I had made a second 20 volt supply, and used cheap capacitors. Apparently, when using high voltages (relatively speaking) the amount of capacitance decreases in cheap, small, ceramic capacitors. I went back to the first supply I made, and added even more capacitance.
The lower trace is the new +20 volt supply, and it’s peak-to-peak noise voltage is about 3mV. But the proof of the pudding is in the eating, so how does it affect the phase noise?
It squashes it like a bug! The above plot is almost textbook for phase noise. The large peak in the center is representing the width of the final filter (I’ll get to that in a later post) and the skirt is caused by traditional phase noise. If I zoom in to the center of that plot it’s easier to see:
Here, I’ve highlighted another common cause of phase noise: PLL loop bandwidth. This is the bandwidth of the filter that smooths out the pulses that come out of the PLL chip.
That’s all I have for now… I’ve tried to make this topic, which is very technical and dry, interesting and accessible to those that haven’t spent the last 5 years trying to build a spectrum analyzer. I hope you’ve enjoyed it.
If you want a much more in-depth and technical analysis, see Scotty’s website.
I haven’t posted for a while. I’m sorry. I was being selfish. I’ve made fantastic progress on my spectrum analyzer build, and it’s so much fun that I haven’t had the will to pull myself away and post about it.
Also, completely unrelated to the build, I’ve experimented with a service called “Cloudflare” as a way to make my site more resilient. It doesn’t, it’s MUCH worse. I’m not happy with it at all. I’ve shut it down, so hopefully once the DNS changes propagate it’ll be more stable.
Anyway, back to topic. The last post about the analyzer was about the ChipKit digital logic controller. That was going very well, so well, in fact, that I was able to finally diagnose an intermittent connection problem between modules. Intermittent problems are always the worst, especially when you don’t trust other components in the system. The reason this is relevant to the discussion at hand is that the problem only manifests when one of the connectors has pressure one one side. I needed a reliable way the hold all the modules in fixed positions.
Since beginning this project, I’ve been inspired by the way that two people built their analyzers. Hans’ is probably my favorite. I took the image below from his photo album in the Yahoo Spectrum Analyzer group.
I love how clean and organized it looks. Much different than most of the others out there. His frame has holes that go all the way through the frame, and he has a back cover that screws on. His coax cabling is made of right-angle soldered-on connectors with what looks like RG-405 hard pipe.
Another inspirational build is Sants. This image is also scraped from the Yahoo group.
This build is most probably the closest to mine. The pockets, or wells, for the component side of the boards don’t go all the way through the substrate. Notice, in both designs, that there is a small lip around the perimeter of each well. This is there to hold the boards and to electrically connect to the ground vias on the perimeter. This design also uses right-angle connectors and hard pipe.
With these designs in mind, I sought out the things I would need. First, of course, was the aluminum itself. I had looked into McMaster-Carr (hopefully this link works), and a 1/2″ thick 12″ square costs about $40. Then, my brother suggested looking on eBay. I was able to find an equivalent sheet for about $30 after shipping.
Once I had a cool hunk of 6061 alloy in my hands, I started designing the layout of the frame. I started with OmniGraffle (it’s like Visio) because I could lay it out to scale, and the connections move in a natural way.
Once the layout was complete, I transcribed the design, complete with all the details into AutoCAD. By this time, about a month passed, and I was able to find someone willing to machine it for me as a favor. I also got a quote from another friend, which was about $250. This is a reasonable cost for something like this, in case you’re looking to duplicate my results.
It took several weeks to get the parts back from the machinist, but the results are totally worth it! The larger hole was cut with a 1/8″ end mill, and the inner pocket was cut with a 1/4″ mill. With the majority of the modules, the inner radius is fine. There were a few exceptions, however.
This photo shows some of the rework I had to do to accommodate a few capacitors right at the edge of the DDS module. It’s very difficult to take a picture of a small notch in a shiny material, but hopefully you can see the cut into the side of this pocket. I made that mostly by making small, successive cuts using an exact-o knife. The PLO reliefs were a bit more aggressive (there is a power header right in the corner), so I had to use a Dremel cutter bit in my drill press.
Once important lesson learned in this process is that 1.2″ or 2.4″ set into a PCB specification is more of a suggestion rather than something that you can count on all that much. I had to sand almost every module to get it to fit. Once that was done, however, everything fit like a glove.
The final piece in the puzzle is the coax. The perfect jumpers that both the other designs featured were definitely something that I wanted. It’s possible to get these right-angle SMA connectors from China for about a dollar a piece, much less than the ~$5 that you’ll spend at Digi-Key.
To make them, all you really need to do is measure the coax sections, strip the ends, and solder…
Soldering around the shield of the coax is the hardest part, and it’s not even that bad.
That’s all there is to it! I’m really happy with how well things turned out. Certainly something to be proud of. Over the next few days, I’m going to try to keep posting about the other advancements. I have a bit of a backlog, so I should be able to keep them coming…
I’ve been able to make solid progress on the spectrum analyzer tonight. I’ve continued using the ChipKit, I’m fairly happy with it at the moment. As I mentioned in the last post, I’ve increased the baud rate on the serial port to 115200 baud. That seems to be the point where the SPI bus speed and the serial port speed are about matched. There’s still plenty of room to increase it, however.
I’ve been progressing in the project by adding one module at a time, and testing as best I can. I’ve got PLO2 (mostly) working, and DDS1 seems to be rock-solid. I’m able to command it to any frequency I want between almost 0 Hz up to 20 MHz. Tonight, I added the ADC to the list of modules that seem to be working. To accomplish this, I had to make two modifications to the ADC. The first was to change it to work with a 3.3v DC supply. This change was trivial, it’s the same as the modification to run off of the power from the PDM. You just remove the old voltage regulator and replace it with a bit of wire. This is necessary because, if it’s powered with 5 volts, the minimum voltage required to mark a digital ’1′ is 3.8 volts. The PIC32 in the chip kit is powered by 3.3 volts, so there’s no way that’s going to happen. In reality, it’s probably going to work, but it’s likely going to give you a headache. Finally, I removed the two transistors that were on the outputs of each ADC. They were there to provide stronger output drivers (the ADCs can only drive their outputs with 500uA). The parallel port requires a pretty healthy amount of current on the status lines. Because it’s being connected directly to a micro controller, these drivers aren’t necessary. Not only that, but they were acting as it they were damaged. With them gone, everything seems to work great!
Now that the ADC and a DDS works, I can begin to use it as a spectrum analyzer… even if it’s only for a very small range of frequencies. For example, I can make a plot of the filter used with the “squarer” in the DDS:
It’s not immediately clear whether this plot makes any sense, I’m hoping that I can get someone in the panel of experts to weigh in on it. It’s reasonable clear that there is a pass band centered around 10.7 MHz, which is what I want. I’m not sure what to think about those steep slopes and the large spike of to the right. None of this may matter, as the DDS will never be tuned out there anyway. It could even be that a harmonic of the DDS output is getting through the passband when it’s tuned there. I really have no idea.
The plot below is from the final resolution bandwidth filter (RBW) that’s used to set the resolution of the analyzer as a whole. I got this filter from one of the MSA experts (thanks, Sam), and I know it performs better than this. Again, I’m wondering if it has this shape due to some quality of the DDS output, or some other factor.
Ultimately, I think these graphs are great, and very encouraging. Even if they’re a bit confusing, it’s nice to be able to put something up on the screen. You might be wondering how I produced them? Well, that’s the embarrassing bit. My cheesy analyzer program (which is really just a way to test the suite of classes I’ve written for communicating with the modules) will spit out text that can be used as a CSV (comma separated values) file that can be read by Excel or Numbers. I used Numbers to create these plots. I think they’re log-scale plots, because the log detector module produces logarithmically increasing voltage given increasing input power, thus I used linear scaling on the Y axis. The Y axis is the raw value from the ADC, and the X axis is the frequency.
I got an email back from Scotty about the graphs I got from my DDS sweeps. The first plot, of the DDS squarer, is normal. The reason it has that shape is best explained in the context of the schematic of that part.
Trace the signal from “OUTA,” it goes through matching network (I think!), then a crystal filter (XF1), and a logic inverter. Basically, the inverter will “snap” on or off once the sine wave from the filter passes a threshold voltage. Once the signal is attenuated to a certain level by the crystal filter, the inverter will no longer trigger. This is the reason for the sharp skirts on either sides of the passband.
Scotty also thinks that the response plot from the RBW filter is indicative of a mismatched input or output. I’m pretty sure it isn’t the actual filter, so I’m going to look into other sources of impedance mismatch.
Not only did Sam agree that the shape of the RBW filter is likely due to the impedance mismatch between the source and the filter, but that I could probably help the situation with an attenuator. I inserted one (with a DC blocking capacitor) between the DDS source and the filter, the plotted it again.
My only concern now is that the filter bandwidth looks much much wider than I expected. I don’t know what the cause of this is. Because I really have no calibration, I don’t know how the “counts” in the ADC map to dBs of signal. Typically, filters are defined by the points to the right and left of the center that are 3dB “down” from the center level. However, I may be able to glean some knowledge from the datasheet.
The slope is ROUGHLY(!) a half a volt per 20dB. I’ll do a better calibration when the code is there, but for now let’s just continue on. Once we know what the slope is, we need to map the counts on the ADC output to volts. I’ve converted the ADC to use 3.3volt power, and it’s a 16 bit device, so there are 65,536 counts (numbers) spanning 3.3 volts, or 19859 counts per volt. In my spreadsheet, I just made a new column that performs this conversion. Finally, because it looks like 2 volts maps to about 10dB. So, I added another column to the spreadsheet, this time subtracting 2 from the volts, divide by .5 and multiply by 20.
Unfortunately, it’s not easy to see where the 3dB points are. Looking at the raw data, I can see that the maximum value is -13.0 dB, so the 3dB points are where -16.0 dB is crossed on each side. On the low side, it’s 10.6989, and on the high side, it’s 10.701360. The resulting 3dB bandwidth is .002 MHz, or 2 kHz. This is exactly the published value. I guess this means that it was a very successful experiment.
Now that I know that trying to use the BusPirate with the 74595′s is basically a non-starter, I’ve moved on to using the ChipKit. The ChipKit is a arduino-like board with a Microchip PIC32 micro controller. The PIC32 is, as the name would imply, a 32 bit processor, running at 80 MHz. That’s pretty impressive, if you ask me. It has a boot loader and software package that makes it more or less compatible with arduino code. I really like that I can just hack something together without all the setting up SFRs (Special Function Registers, or the bane of embedded device programmers existence).
Anyway, I’ve developed a simple “sketch” (program in arduino terminology) that accepts serial commands and executes SPI transfers using a set of pins through the 74595′s. You can kinda see what’s happening in the logic analyzer trace above. The top three traces are the SPI commands to the PLO module. The middle two are the serial in and out of the chip kit. The bottom three are the SPI commands to the 74595′s. I had to zoom out far enough that you can’t see what the serial or bottom SPI contents are, but it’s basically “$,s,A,B,C,L,DDD…” where A, B, and C are the pins for SPI Chip Select, Clock and Data, L is the length of the transfer in bytes and DDD… is the contents of the transfer. Currently, the limiting factor is the serial communication (by that I mean UART, not SPI), but I’m only using 9600 baud in this example. The ChipKit uses an FT232R USB-Serial converter that is good into the megabaud. In the future I’ll experiment with higher baud rates.
That’s basically, all. I just wanted to post and say that it works. By the way, the PLO module happily accepted its commands and tuned to 1024 MHz. :)